1. Technical Field
Embodiments of the present invention generally relate to point-to-point data links. More particularly, embodiments relate to the retraining of receivers in a derived clock data link.
2. Discussion
A data link is a point-to-point interconnect between agents, where in a given transaction one agent is a “transmitter” and the other agent is a “receiver”. Example data links include a processor writing data to a disk drive, processors on separate boards in a computer system transferring data between one another, processors on the same board transferring data, etc. With any data link, in order for two agents to communicate, both agents must agree on the exact timing for sending and receiving data. This agreement is commonly known as the clocking scheme in link design. While several clocking schemes are used in industry, there remains considerable room for improvement.
For example, in a clocking scheme known as the “common clock” scheme, all agents in the interconnect share a single clock when sending and receiving data. Transmission protocol defines when transmitters send data and when receivers sample the data. Although such a scheme eliminates the need for synchronization between agents, the range of available clock frequencies can be limited because the clock must be propagated throughout the system for all agents to see and use.
In the “source synchronous” clocking scheme, the clock signal is sent along with the data signal. Such an approach relaxes the clock frequency limitations associated with the common clock scheme, but may increase the amount of non-payload data to be sent between the transmitter and receiver.
The “embedded” clocking scheme improves on the source synchronous clocking scheme by embedding the clock signal in the data transfer. As a result, the need for external clock signals can be eliminated. Receivers recover the clock from the data signal by interpolating from the transitions in data signals. A transition is defined as a change from logical “0” to logical “1” or vice versa. Due to environmental drift, however, each receiver must retrain its interpolator periodically in order to stay synchronized with the transmitter.
Certain embedded clocking schemes, such as 8-bit/10-bit (8B10B), address the concern over drift by attempting to maintain a certain minimum transition density for the outgoing data signal. Such a minimum transition density might be defined in terms of a minimum of “n” transitions over a period of “m” cycles, wherein n is a small integer between 2 and 5 and m is a larger integer between 1024 and 4096. These types of embedded clocking schemes allocate a relatively large amount of the signal to guarantee the minimum transition density for the entire data signal as well as other features such as DC balance and running disparity. DC balance is the property of having an equal number of ones and zeroes. For a signal to have good DC balance means there is a low frequency cutoff to the spectrum of the data signal below which no useful information is carried. Such a frequency cutoff can sometimes provide significant filtering and circuit design advantages. Running disparity helps the transmitter achieve DC balance by defining an ongoing maximum difference between the number of ones and zeroes. Maintaining DC balance and running disparity restraints for the entire data signal can provide a high quality, signal, but can also lead to an undesirably high amount of overhead. Indeed, the overhead associated with conventional 8B10B schemes is in the order of 20 percent. Although such an overhead may be acceptable under certain circumstances, there are some environments for which improvement is needed. For example, when transmitting small amounts of data over short distances and at high speeds, as in processor-to-processor communication on the same board or on nearby boards, the overhead associated with DC balance may not be worthwhile. There is therefore a need for a clocking scheme that provides for relatively low overhead.